a. Field of the Invention
The present invention pertains generally to parallel interfaces and specifically to deskewing incoming timing signals.
b. Description of the Background
Ultra320 SCSI is a parallel interface standard for the connection of computer peripherals such as hard disk storage devices. The Ultra320 SCSI interface is a parallel interface containing multiple wires that simultaneously transmit data and clock signals. The inevitable result is that wire lengths and impedance are different for the signal wires so that one signal reaches a destination before another. The high speed of the Ultra320 SCSI interface causes such differences in signal timing to be a problem to the point where a training pattern is used to measure and correct the imbalances in the SCSI bus. Particularly, the training pattern is used to find delays on any of the particular wires. If such delays are found, compensations are made in future transmissions based on the delays measured during the training pattern.
During a transmission, a clock signal and several data signals are transmitted simultaneously. The receiver may read the data after a half-period delay in the clock signal. A method to determine the amount of delay to apply would be to measure the period of the clock and read the data at exactly half of that period. Any offset from the half period measurement is known as the deskew value.
In chip-based implementations of the Ultra320 SCSI standard, the signals may not be reachable to probe with an oscilloscope or other external measurement tool because the receiver deskew logic are inside the chip. Hence, the designer may need alternative ways of optimizing the deskew parameters.
It would therefore be advantageous to provide a system and method for determining the optimum deskew for reading the data signals when the signals are within a chip and cannot be physically probed with a measurement device. It would be further advantageous to be able to optimize the deskew for an assembled system.